Bibtest

Articles (12)

• György Pilászy, György Rácz, Péter Arató (2014) The Effect of Latency Increasing on the Realisation Cost in High Level Synthesis of Pipeline Systems. Periodica Polytechnica Electrical Engineering and Computer Science 58 (2) pp. 37–42. doi web abstract This paper examines the effects of increasing the latency in pipeline systems. The high level synthesis methods focus on the pipeline throughput only, and the latency is an output parameter. The proposed method is capable for reducing the cost of the implementation by increasing the latency at the same throughput. The essence of the proposed method is that an increase in the latency may increase the mobility ranges of the processing units. Thus, the increased degrees of freedom may cause better implementation by affecting the scheduling and allocation steps. An impact assessment algorithm for calculating proper latency increment range is also presented. bibtex

  @article{Pilaszy2014,
  abstract = {This paper examines the effects of increasing the latency in pipeline systems. The high level synthesis methods focus on the pipeline throughput only, and the latency is an output parameter. The proposed method is capable for reducing the cost of the implementation by increasing the latency at the same throughput. The essence of the proposed method is that an increase in the latency may increase the mobility ranges of the processing units. Thus, the increased degrees of freedom may cause better implementation by affecting the scheduling and allocation steps. An impact assessment algorithm for calculating proper latency increment range is also presented.},
  author = {Pilászy, György and Rácz, György and Arató, Péter},
  doi = {10.3311/PPee.7024},
  issn = {20645260},
  journal = {Periodica Polytechnica Electrical Engineering and Computer Science},
  keywords = {BME,CAD,HLS,Pipeline,Pipelining,article-ARRAY,cad,embedded systems,hls,latency time,microcontroller,multiprocessing,pipelining},
  mendeley-tags = {BME,HLS,Pipeline,article-ARRAY},
  number = {2},
  pages = {37--42},
  title = {{The Effect of Latency Increasing on the Realisation Cost in High Level Synthesis of Pipeline Systems}},
  url = {http://pp.bme.hu/eecs/article/download/7024/6464},
  volume = {58},
  year = {2014}
  }

• Péter Arató, Gergely Suba (2014) Data Flow Graph Generation of Nested Loops from Imperative High Level Description. SCIENTIFIC BULLETIN of The POLITEHNICA University of Timişoara, Romania 59(73) (2) pp. 123–130. web abstract The first essential task in high-level or systemlevel synthesis is to process the source code of the input task and produce an intermediate representation. This representation is a data flow graph description in most cases. The further steps attempt optimizing the data flow graph and transform the algorithm into an output representation (usually Verilog, VHDL for FPGA target, and ASM, C for CPU target). Nowadays, the imperative languages are dominant in the field of software technology. The aim of this paper is to present a method for compiling an imperative language description into a hierarchical data flow graph, which is able to represent also nested loops in a beneficial way. For practical reasons, C has been chosen as input for demonstrating the method, because it is one of the most widely used language in software and hardware design field. For parsing and analyzing the C code, the frontend of the GNU Compiler Collection (GCC) is applied. The existing data flow graph generation solutions suffer from the difficulty of handling loop nest hierarchy. We present a method, which transforms systematically the GCC produced control- and data flow like description (called GIMPLE) into a hierarchical data flow graph representation by handling the nested loops. The whole method is illustrated on a C source code example and on the intermediate descriptions of the conversation steps. bibtex

  @article{Arato2015,
  abstract = {The first essential task in high-level or systemlevel synthesis is to process the source code of the input task and produce an intermediate representation. This representation is a data flow graph description in most cases. The further steps attempt optimizing the data flow graph and transform the algorithm into an output representation (usually Verilog, VHDL for FPGA target, and ASM, C for CPU target). Nowadays, the imperative languages are dominant in the field of software technology. The aim of this paper is to present a method for compiling an imperative language description into a hierarchical data flow graph, which is able to represent also nested loops in a beneficial way. For practical reasons, C has been chosen as input for demonstrating the method, because it is one of the most widely used language in software and hardware design field. For parsing and analyzing the C code, the frontend of the GNU Compiler Collection (GCC) is applied. The existing data flow graph generation solutions suffer from the difficulty of handling loop nest hierarchy. We present a method, which transforms systematically the GCC produced control- and data flow like description (called GIMPLE) into a hierarchical data flow graph representation by handling the nested loops. The whole method is illustrated on a C source code example and on the intermediate descriptions of the conversation steps.},
  author = {Arató, Péter and Suba, Gergely},
  journal = {SCIENTIFIC BULLETIN of The POLITEHNICA University of Timişoara, Romania},
  keywords = {GCC,GIMPLE,data flow graph,high-level synthesis,nested loops,static single assignment,system-level synthesis},
  number = {2},
  pages = {123--130},
  title = {{Data Flow Graph Generation of Nested Loops from Imperative High Level Description}},
  url = {http://www.ac.upt.ro/journal/article.php?v=59(73)&vn=2&n=11},
  volume = {59(73)},
  year = {2014}
  }

• Gergely Suba (2014) Hierarchical Pipelining of Nested Loops in High-Level Synthesis. Periodica Polytechnica Electrical Engineering and Computer Science 58 (3) pp. 81–91. doi web abstract Pipelining of the nested loops is very important in increasing the throughput of a system developed by a high-level synthesis tool. The most pipelining methods can handle only single loops. Therefore, nested loops are converted into a single loop, called loop flattened loop. In consequence, i.e. the sequential loops cannot be implemented in separate pipeline stages. This constraint limits the throughput. In this paper, a novel method are presented for nested loops by implementing to avoid this limitation. The method has the advantage that the desired restart time of the whole system can be given as an input parameter. The necessity of the pipeline scheduling on each loop hierarchy level can also be determined by this method. A novel multirate dataflow graph is also introduced for modeling the nested loops in an easy and abstract way. bibtex

  @article{Suba2014,
  abstract = {Pipelining of the nested loops is very important in increasing the throughput of a system developed by a high-level synthesis tool. The most pipelining methods can handle only single loops. Therefore, nested loops are converted into a single loop, called loop flattened loop. In consequence, i.e. the sequential loops cannot be implemented in separate pipeline stages. This constraint limits the throughput. In this paper, a novel method are presented for nested loops by implementing to avoid this limitation. The method has the advantage that the desired restart time of the whole system can be given as an input parameter. The necessity of the pipeline scheduling on each loop hierarchy level can also be determined by this method. A novel multirate dataflow graph is also introduced for modeling the nested loops in an easy and abstract way.},
  author = {Suba, Gergely},
  doi = {10.3311/PPee.7610},
  issn = {20645260},
  journal = {Periodica Polytechnica Electrical Engineering and Computer Science},
  keywords = {hls,multi-rate,nested loops,pipeline scheduling,sdf},
  number = {3},
  pages = {81--91},
  title = {{Hierarchical Pipelining of Nested Loops in High-Level Synthesis}},
  url = {http://www.pp.bme.hu/eecs/article/download/7610/6508},
  volume = {58},
  year = {2014}
  }

• Péter Arató, Gábor Kocza (2014) Loop-free Decomposition in High-Level Synthesis. SCIENTIFIC BULLETIN of The POLITEHNICA University of Timişoara, Romania 59(73) (2) pp. 99–104. web abstract Decomposition of data flow-like graphs into graphs with smaller number of nodes is a common task in high-level synthesis. However, it is desirable to ensure that a loop-free graph remains loop-free after the decomposition. We propose a decomposition algorithm that generates the set of cuts that define loop-free partitions of the originally loop-free graph. We extend the algorithm to be able to take optimization criteria into consideration. Weights are associated to the edges of the graph, and the decomposition algorithm generates a partitioning of the graph such that the sum of the weights of the edges along the cuts is minimal. The loop-free property of the resulting graph is proved if the initial graph is loop-free. The algorithms are demonstrated on simple examples. bibtex

  @article{Arato2014,
  abstract = {Decomposition of data flow-like graphs into graphs with smaller number of nodes is a common task in high-level synthesis. However, it is desirable to ensure that a loop-free graph remains loop-free after the decomposition. We propose a decomposition algorithm that generates the set of cuts that define loop-free partitions of the originally loop-free graph. We extend the algorithm to be able to take optimization criteria into consideration. Weights are associated to the edges of the graph, and the decomposition algorithm generates a partitioning of the graph such that the sum of the weights of the edges along the cuts is minimal. The loop-free property of the resulting graph is proved if the initial graph is loop-free. The algorithms are demonstrated on simple examples.},
  author = {Arató, Péter and Kocza, Gábor},
  journal = {SCIENTIFIC BULLETIN of The POLITEHNICA University of Timişoara, Romania},
  keywords = {directed acyclic graph,graph cutting,heterogeneous systems,system-level synthesis},
  number = {2},
  pages = {99--104},
  title = {{Loop-free Decomposition in High-Level Synthesis}},
  url = {http://www.ac.upt.ro/journal/article.php?v=59(73)&vn=2&n=8},
  volume = {59(73)},
  year = {2014}
  }

• György Pilászy, György Rácz, Péter Arató (2013) Communication Time Estimation in High Level Synthesis. Periodica Polytechnica Electrical Engineering and Computer Science 57 (4) pp. 99. doi web abstract The high level synthesis (HLS) tools may result in a multiprocessing structure, where the time demand of the interchip data transfer (briefly the communication) between the processing units (hardware or software) is determined exactly only after the task-allocation. However, a realistic preliminary estimation of the communication time would help to shape the scheduling and the allocation procedures just for attempting to minimize the communication times in the final structure. Compared to the task-execution times of the processing units, especially significant communication times are required by the serial communication interfaces which are frequently used in microcontroller systems. This paper presents an estimation method by analysing four well-known serial communication interfaces (SPI, CAN, I2C, UART). bibtex

  @article{Pilaszy2013,
  author = {Pilászy, György and Rácz, György and Arató, Péter},
  doi = {10.3311/PPee.7413},
  issn = {0031-532X},
  journal = {Periodica Polytechnica Electrical Engineering and Computer Science},
  keywords = {BME,HLS},
  number = {4},
  pages = {99},
  title = {{Communication Time Estimation in High Level Synthesis}},
  url = {http://www.pp.bme.hu/eecs/article/download/7413/6314},
  volume = {57},
  year = {2013},
  abstract = {The high level synthesis (HLS) tools may result in a multiprocessing structure, where the time demand of the interchip data transfer (briefly the communication) between the processing units (hardware or software) is determined exactly only after the task-allocation. However, a realistic preliminary estimation of the communication time would help to shape the scheduling and the allocation procedures just for attempting to minimize the communication times in the final structure. Compared to the task-execution times of the processing units, especially significant communication times are required by the serial communication interfaces which are frequently used in microcontroller systems. This paper presents an estimation method by analysing four well-known serial communication interfaces (SPI, CAN, I2C, UART).}, 
  }

• Péter Arató, Bence Csák (2008) Pipeline mode in C-based direct hardware implementation. Periodica Polytechnica Electrical Engineering 52 (3-4) pp. 197-208. doi web abstract In this paper a methodology is presented that enables the pipeline function of hardware blocks created by C-based direct hardware design. The method is embedded into the C-based design methodology worked out by the authors earlier. This pipeline enabling method is rather flexible, needs no special efforts. With the help of a simple state-machine-based entity, blocks of different execution times can build up the pipeline, even with data-dependent duration. A data-spreading technique solves data consistency. Pipeline sectioning - chosing the right and balanced granularity versus pipelining overhead - is an optimisation matter. Simulation results prove the correctness of the method. bibtex

  @article{Arato2008,
   abstract = {In this paper a methodology is presented that enables the pipeline function of hardware blocks created by C-based direct hardware design. The method is embedded into the C-based design methodology worked out by the authors earlier. This pipeline enabling method is rather flexible, needs no special efforts. With the help of a simple state-machine-based entity, blocks of different execution times can build up the pipeline, even with data-dependent duration. A data-spreading technique solves data consistency. Pipeline sectioning - chosing the right and balanced granularity versus pipelining overhead - is an optimisation matter. Simulation results prove the correctness of the method.},
   author = {Arató, Péter and Csák, Bence},
   doi = {10.3311/pp.ee.2008-3-4.08},
   issn = {0031-532X},
   journal = {Periodica Polytechnica Electrical Engineering},
   keywords = {c-based design,component based design,hardware-software codesign,parallel,pipelining,processing,reuse},
   number = {3-4},
   pages = {197-208},
   title = {{Pipeline mode in C-based direct hardware implementation}},
   url = {http://www.pp.bme.hu/ee/2008_3-4/ee2008_3-4_08.html},
   volume = {52},
   year = {2008}
  }

• Zoltán Ádám Mann, András Orbán, Péter Arató (dec 2007) Finding optimal hardware/software partitions. Form. Methods Syst. Des. 31 (3) pp. 241–263. Kluwer Academic Publishers. Hingham, MA, USA. doi web _ bibtex

  @article{Mann:2007:FOH:1315662.1315669,
   author = {Mann, Zoltán Ádám and Orbán, András and Arató, Péter},
   title = {Finding optimal hardware/software partitions},
   journal = {Form. Methods Syst. Des.},
   issue_date = {December  2007},
   volume = {31},
   number = {3},
   month = dec,
   year = {2007},
   issn = {0925-9856},
   pages = {241--263},
   numpages = {23},
   url = {http://dx.doi.org/10.1007/s10703-007-0039-0},
   doi = {10.1007/s10703-007-0039-0},
   acmid = {1315669},
   publisher = {Kluwer Academic Publishers},
   address = {Hingham, MA, USA},
   keywords = {Branch-and-bound, Hardware/software co-design, Hardware/software partitioning, Integer linear programming},
  }

• Péter Arató, Zoltán Ádám Mann, Andás Orbán (dec 2005) Time-constrained scheduling of large pipelined datapaths. J. Syst. Archit. 51 (12) pp. 665–687. Elsevier North-Holland, Inc.. New York, NY, USA. doi web _ bibtex

  @article{Arato:2005:TSL:1127128.1127130,
   author = {Arató, Péter and Mann, Zoltán Ádám and Orbán, Andás},
   title = {Time-constrained scheduling of large pipelined datapaths},
   journal = {J. Syst. Archit.},
   issue_date = {December 2005},
   volume = {51},
   number = {12},
   month = dec,
   year = {2005},
   issn = {1383-7621},
   pages = {665--687},
   numpages = {23},
   url = {http://dx.doi.org/10.1016/j.sysarc.2005.02.001},
   doi = {10.1016/j.sysarc.2005.02.001},
   acmid = {1127130},
   publisher = {Elsevier North-Holland, Inc.},
   address = {New York, NY, USA},
   keywords = {allocation, constraint logic programming, genetic algorithm, high-level synthesis, pipeline, scheduling},
  }

• Péter Arató, Zoltán Ádám Mann, András Orbán (jan 2005) Algorithmic aspects of hardware/software partitioning. ACM Trans. Des. Autom. Electron. Syst. 10 (1) pp. 136–156. ACM. New York, NY, USA. doi web _ bibtex

  @article{Arato:2005:AAH:1044111.1044119,
   author = {Arató, Péter and Mann, Zoltán Ádám and Orbán, András},
   title = {Algorithmic aspects of hardware/software partitioning},
   journal = {ACM Trans. Des. Autom. Electron. Syst.},
   issue_date = {January 2005},
   volume = {10},
   number = {1},
   month = jan,
   year = {2005},
   issn = {1084-4309},
   pages = {136--156},
   numpages = {21},
   url = {http://doi.acm.org/10.1145/1044111.1044119},
   doi = {10.1145/1044111.1044119},
   acmid = {1044119},
   publisher = {ACM},
   address = {New York, NY, USA},
   keywords = {Hardware/software partitioning, graph algorithms, graph bipartitioning, hardware/software codesign, optimization},
  }

• Péter Arató, Zoltán Ádám Mann, András Orbán (apr 2005) Extending component-based design with hardware components. Science of Computer Programming 56 (1-2) pp. 23–39. Elsevier North-Holland, Inc.. Amsterdam, The Netherlands, The Netherlands. doi web abstract In order to cope with the increasing complexity of system design, component-based software engineering advocates the reuse and adaptation of existing software components. However, many applications—particularly embedded systems—consist of not only software, but also hardware components. Thus, component-based design should be extended to systems with both hardware and software components. Such an extension is not without challenges though. The extended methodology has to consider hard constraints on performance as well as different cost factors. Also, the dissimilarities between hardware and software (such as level of abstraction, communication primitives, etc.) have to be resolved. In this paper, the authors propose such an extended component-based design methodology to include hardware components as well. This methodology allows the designer to work at a very high level of abstraction, where the focus is on functionality only. Non-functional constraints are specified in a declarative manner, and the mapping of components to hardware or software is determined automatically based on those constraints in the so-called hardware/software partitioning step. Moreover, a tool is presented supporting the new design methodology. Beside automating the partitioning process, this tool also checks the consistency between hardware and software implementations of a component. The authors also present a case study to demonstrate the applicability of the outlined concepts. bibtex

  @article{Arato:2005:ECD:1072118.1072121,
   author = {Arató, Péter and Mann, Zoltán Ádám and Orbán, András},
   title = {Extending component-based design with hardware components},
   journal = {Science of Computer Programming},
   issue_date = {April 2005},
   volume = {56},
   number = {1-2},
   month = apr,
   year = {2005},
   issn = {0167-6423},
   pages = {23--39},
   numpages = {17},
   note = "<ce:title>New Software Composition Concepts</ce:title>",
   url = "http://www.sciencedirect.com/science/article/pii/S0167642304001753",
   doi = {10.1016/j.scico.2004.11.003},
   acmid = {1072121},
   publisher = {Elsevier North-Holland, Inc.},
   address = {Amsterdam, The Netherlands, The Netherlands},
   keywords = {component-based design, hardware/software co-design, hardware/software partitioning},
   abstract = "In order to cope with the increasing complexity of system design, component-based software engineering advocates the reuse and adaptation of existing software components. However, many applications—particularly embedded systems—consist of not only software, but also hardware components. Thus, component-based design should be extended to systems with both hardware and software components.
   
  Such an extension is not without challenges though. The extended methodology has to consider hard constraints on performance as well as different cost factors. Also, the dissimilarities between hardware and software (such as level of abstraction, communication primitives, etc.) have to be resolved.
   
  In this paper, the authors propose such an extended component-based design methodology to include hardware components as well. This methodology allows the designer to work at a very high level of abstraction, where the focus is on functionality only. Non-functional constraints are specified in a declarative manner, and the mapping of components to hardware or software is determined automatically based on those constraints in the so-called hardware/software partitioning step.
   
  Moreover, a tool is presented supporting the new design methodology. Beside automating the partitioning process, this tool also checks the consistency between hardware and software implementations of a component.
   
  The authors also present a case study to demonstrate the applicability of the outlined concepts."
  }

• Péter Arató, Tamás Visegrády (1998) Effective graph generation from VHDL descriptions. Microelectronics Journal 29 (3) pp. 113 - 121. doi web abstract The transformation between a problem description and a data dependency graph is a step that results in a significant reduction of freedom during high-level synthesis. This paper presents an evaluation of different graph generation methods and makes a suggestion on the methods to be employed in the solution of such a problem. High-level synthesis takes its input written in an artificial language, i.e. VHDL or one of several similar languages [1]. These descriptions take the form of functions which must be transformed to a hardware realization using the steps of initial allocation, scheduling and allocation. bibtex

  @article{Arató1998113,
  title = "Effective graph generation from VHDL descriptions",
  journal = "Microelectronics Journal",
  volume = "29",
  number = "3",
  pages = "113 - 121",
  year = "1998",
  note = "",
  issn = "0026-2692",
  doi = "10.1016/S0026-2692(97)00037-2",
  url = "http://www.sciencedirect.com/science/article/pii/S0026269297000372",
  author = "Péter Arató and Tamás Visegrády",
  abstract = "The transformation between a problem description and a data dependency graph is a step that results in a significant reduction of freedom during high-level synthesis. This paper presents an evaluation of different graph generation methods and makes a suggestion on the methods to be employed in the solution of such a problem. High-level synthesis takes its input written in an artificial language, i.e. VHDL or one of several similar languages [1]. These descriptions take the form of functions which must be transformed to a hardware realization using the steps of initial allocation, scheduling and allocation."
  }

• Péter Arató, lstván Béres, Andrzej Rucinski, Robert Davis, Roy Torbert (1994) A high-level datapath synthesis method for pipelined structures. Microelectronics Journal 25 (3) pp. 237 - 247. doi web abstract This paper presents a model and a method for the high-level datapath synthesis of pipelined ASIC architectures, starting with a behavioural description of the system consisting of theoretical operational units with arbitrary operation duration. The method calculates the minimal number of buffers to be inserted, optimally selects the number of types of additional operational units, and determines the minimal number of required copies. The aim of the procedure is to ensure a latency which can be given in advance, and could not be achieved without additional buffers and extra copies of the operational units. The method provides a solution to the resource allocation problem by establishing a compatibility relation between the concurrent operations. The constraints for the types of processors to be applied can vary, depending upon the hardware resources. bibtex

  @article{Arató1994237,
  title = "A high-level datapath synthesis method for pipelined structures",
  journal = "Microelectronics Journal",
  volume = "25",
  number = "3",
  pages = "237 - 247",
  year = "1994",
  note = "",
  issn = "0026-2692",
  doi = "10.1016/0026-2692(94)90015-9",
  url = "http://www.sciencedirect.com/science/article/pii/0026269294900159",
  author = "Péter Arató and lstván Béres and Andrzej Rucinski and Robert Davis and Roy Torbert",
  abstract = "This paper presents a model and a method for the high-level datapath synthesis of pipelined ASIC architectures, starting with a behavioural description of the system consisting of theoretical operational units with arbitrary operation duration. The method calculates the minimal number of buffers to be inserted, optimally selects the number of types of additional operational units, and determines the minimal number of required copies.
   
  The aim of the procedure is to ensure a latency which can be given in advance, and could not be achieved without additional buffers and extra copies of the operational units. The method provides a solution to the resource allocation problem by establishing a compatibility relation between the concurrent operations. The constraints for the types of processors to be applied can vary, depending upon the hardware resources."
  }

Books (1)

• Péter Arató, Visegrády Tamás, István Jankovits (2001) High Level Synthesis of Pipelined Datapaths. John Wiley & Sons, Inc.. New York, NY, USA. web _ bibtex

  @book{arato,
   author = {Arató, Péter and Tamás, Visegrády and Jankovits, István},
   title = {High Level Synthesis of Pipelined Datapaths},
   year = {2001},
   isbn = {0471495824},
   publisher = {John Wiley & Sons, Inc.},
   address = {New York, NY, USA},
   url = {http://dl.acm.org/citation.cfm?id=558618},
  }

In Proceedings (12)

• Gergely Suba, Péter Arató (2015) Concept of the system-level synthesis framework PipeComp. In WAIT 2015 : Workshop on the Advances of Information Technology. Budapest. web abstract In this paper, the new system-level synthesis (SLS) framework PipeComp is introduced. The purpose of PipeComp is to compile source codes to target languages of different architectures, e.g. to hardware description or soft- ware program code. PipeComp is a three-layer architecture framework, it contains frontends, middle-ends and backends. The main different between PipeComp and the existing SLS solutions is that it has a dataflow graph in- termediate language among the layers. Some specific modules are already implemented in PipeComp: imperative, functional and graphical frontends, pipeline scheduler and decomposition middle-ends, program code, hardware description and visual backends, which are introduced briefly in this paper. bibtex

  @inproceedings{Suba2015,
  abstract = {In this paper, the new system-level synthesis (SLS) framework PipeComp is introduced. The purpose of PipeComp is to compile source codes to target languages of different architectures, e.g. to hardware description or soft- ware program code. PipeComp is a three-layer architecture framework, it contains frontends, middle-ends and backends. The main different between PipeComp and the existing SLS solutions is that it has a dataflow graph in- termediate language among the layers. Some specific modules are already implemented in PipeComp: imperative, functional and graphical frontends, pipeline scheduler and decomposition middle-ends, program code, hardware description and visual backends, which are introduced briefly in this paper.},
  address = {Budapest},
  author = {Suba, Gergely and Arató, Péter},
  booktitle = {WAIT 2015 : Workshop on the Advances of Information Technology},
  title = {{Concept of the system-level synthesis framework PipeComp}},
  year = {2015},
  url = {http://hls.iit.bme.hu/lib/exe/fetch.php/hu/pipecomp.pdf},
  url2 = {http://hls.iit.bme.hu/lib/exe/fetch.php/hu/concept_of_the_system-level_synthesis_framework_pipecomp.pdf}
  }

• Péter Arató, Dániel András Drexler, Gábor Kocza (may 2014) A method for avoiding loops while decomposing the task description graph in system-level synthesis. In 2014 IEEE 9th IEEE International Symposium on Applied Computational Intelligence and Informatics (SACI). pp. 231–235. IEEE. doi web abstract In system-level synthesis, the graph describing the task may consist of a great number of vertices, thus the design algorithms (e.g. hardware-software partitioning, pipeline synthesis, etc.) may become extremely complicated. This difficulty is relaxed by decomposing the task description graph that is usually unavoidable in system-level synthesis. The decomposing algorithms unite certain vertices of the graph, thus the resulting graph consists of less vertices. However, loops may appear in the decomposed graph, even if the original graph was loop-free, that endangers the efficiency of the design algorithms. We propose an algorithm that generates allowable cuts. We prove that any decomposition made along these cuts always yields a loop-free graph. The method is demonstrated on a simple example. Incorporating optimization criteria in the cut generation is also discussed. bibtex

  @inproceedings{Arato2014,
  abstract = {In system-level synthesis, the graph describing the task may consist of a great number of vertices, thus the design algorithms (e.g. hardware-software partitioning, pipeline synthesis, etc.) may become extremely complicated. This difficulty is relaxed by decomposing the task description graph that is usually unavoidable in system-level synthesis. The decomposing algorithms unite certain vertices of the graph, thus the resulting graph consists of less vertices. However, loops may appear in the decomposed graph, even if the original graph was loop-free, that endangers the efficiency of the design algorithms. We propose an algorithm that generates allowable cuts. We prove that any decomposition made along these cuts always yields a loop-free graph. The method is demonstrated on a simple example. Incorporating optimization criteria in the cut generation is also discussed.},
  author = {Arató, Péter and Drexler, Dániel András and Kocza, Gábor},
  booktitle = {2014 IEEE 9th IEEE International Symposium on Applied Computational Intelligence and Informatics (SACI)},
  doi = {10.1109/SACI.2014.6840066},
  isbn = {978-1-4799-4694-5},
  keywords = {Algorithm design and analysis,Computational intelligence,Conferences,Hardware,Informatics,Partitioning algorithms,Software,cut generation,data flow analysis,decomposed graph,design algorithms,directed acyclic graph,graph cutting,graph theory,loop avoidance,loop-free decomposition,loop-free graph,optimisation,optimization criteria,system-level synthesis,task description graph decomposition},
  month = may,
  pages = {231--235},
  publisher = {IEEE},
  shorttitle = {Applied Computational Intelligence and Informatics},
  title = {{A method for avoiding loops while decomposing the task description graph in system-level synthesis}},
  url = {http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6840066},
  year = {2014}
  }

• Péter Arató, Gergely Suba (may 2014) A data flow graph generation method starting from C description by handling loop nest hierarchy. In IEEE 9th IEEE International Symposium on Applied Computational Intelligence and Informatics (SACI). pp. 269–274. IEEE. doi web abstract The system-level synthesis of complex hardware or multiprocessing systems start from some kind of a task description formalized usually in a high-level programming language. For this purpose, the C language is used very often. The further steps of the synthesis procedure are based on some kind of data flow graph representation of the task. Therefore, transforming C-code into a graph representation (as systematic as possible) is crucial step in the whole synthesis procedure. One of the difficulty in formalizing transformation algorithm is that the C-code may contain nested loops. The existing solutions suffer from the difficulty of handling such loop nest hierarchy. We present a method, which can solve systematically the transformation from the C-code into a multi-rate data flow graph representation by handling the nested loops. The main steps of the method are illustrated by a simple example. bibtex

  @inproceedings{Arato2014,
  abstract = {The system-level synthesis of complex hardware or multiprocessing systems start from some kind of a task description formalized usually in a high-level programming language. For this purpose, the C language is used very often. The further steps of the synthesis procedure are based on some kind of data flow graph representation of the task. Therefore, transforming C-code into a graph representation (as systematic as possible) is crucial step in the whole synthesis procedure. One of the difficulty in formalizing transformation algorithm is that the C-code may contain nested loops. The existing solutions suffer from the difficulty of handling such loop nest hierarchy. We present a method, which can solve systematically the transformation from the C-code into a multi-rate data flow graph representation by handling the nested loops. The main steps of the method are illustrated by a simple example.},
  author = {Arató, Péter and Suba, Gergely},
  booktitle = {IEEE 9th IEEE International Symposium on Applied Computational Intelligence and Informatics (SACI)},
  doi = {10.1109/SACI.2014.6840074},
  isbn = {978-1-4799-4694-5},
  keywords = {BME,C,C description,C language,C-code,Computational intelligence,Data models,Dataflow,Educational institutions,Flow graphs,HLS,Hardware,Indexes,Informatics,Loop,Nested loops,article-ARRAY,article-ARRAY-1,article-SACI,data flow graphs,formal specification,graph representation,high-level programming language,loop nest hierarchy,multiprocessing systems,multirate data flow graph representation,nested loops,program compilers,system-level synthesis,task description,transformation algorithm formalization},
  month = may,
  pages = {269--274},
  publisher = {IEEE},
  shorttitle = {Applied Computational Intelligence and Informatics},
  title = {{A data flow graph generation method starting from C description by handling loop nest hierarchy}},
  url = {http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6840074},
  year = {2014}
  }

• Gergely Suba, Péter Arató (2013) A new method for transforming algorithm into VHDL by starting from a Haskell functional language description. In Middle-European Conference on Applied Theoretical Computer Science. web abstract In the field of computer engineering, there are a lot of prob- lems that are too time-consuming like biological or physical calculations and that’s why they have to be implemented using special hardware structures. Usually, these hardware structures are described in HDL (Hardware Description Lan- guage). Developing in HDL languages is not as efficient as it would be in case of software languages due to its low level structures. The aim of this work is to implement and test a method (a compiler program), where the starting point is a code written in the functional language Haskell and the output is the same algorithm in VHDL (a kind of HDL) language. The main advantage of the novel method presented in this paper is that it generates a synthesizable VHDL description from Haskell code automatically for FPGA implementation. The method introduced in this paper can solve two sepa- rate problems: 1) running algorithms effectively in FPGA, 2) development of digital hardware implementing a speci- fied function. We demonstrate the efficiency of the method through practical examples like a part of the MP3 decoding algorithm. bibtex

  @inproceedings{Suba2013,
  abstract = {In the field of computer engineering, there are a lot of prob- lems that are too time-consuming like biological or physical calculations and that’s why they have to be implemented using special hardware structures. Usually, these hardware structures are described in HDL (Hardware Description Lan- guage). Developing in HDL languages is not as efficient as it would be in case of software languages due to its low level structures. The aim of this work is to implement and test a method (a compiler program), where the starting point is a code written in the functional language Haskell and the output is the same algorithm in VHDL (a kind of HDL) language. The main advantage of the novel method presented in this paper is that it generates a synthesizable VHDL description from Haskell code automatically for FPGA implementation. The method introduced in this paper can solve two sepa- rate problems: 1) running algorithms effectively in FPGA, 2) development of digital hardware implementing a speci- fied function. We demonstrate the efficiency of the method through practical examples like a part of the MP3 decoding algorithm.},
  author = {Suba, Gergely and Arató, Péter},
  booktitle = {Middle-European Conference on Applied Theoretical Computer Science},
  title = {{A new method for transforming algorithm into VHDL by starting from a Haskell functional language description}},
  url = {http://www.hippocampus.si/ISBN/978-961-6984-21-8/index.html},
  url2 = {http://www.hippocampus.si/ISBN/978-961-6984-20-1.pdf},
  year = {2013}
  }

• Péter Arató, Gábor Kocza, István Loványi, László Vajta (feb. 2008) Hardware-software Codesing of Feature Tracking Algorithms. In Intelligent Engineering Systems, 2008. INES 2008. International Conference on. pp. 41 -45. doi abstract Relative motion of camera and environment results in such visual cues, which may characterize 3D motion as well as the 3D structure of the a-priori unknown environment. 3D navigation includes both tasks: motion and 3D structure estimation. Earlier we showed that navigation can be based on the KLT algorithm where feature-type visual cues (e.g. corners) are selected and tracked throughout the video frame sequence. Reliability and real-time feature of 3D reconstruction mainly depends on the specificities of selected algorithms and design metrics of implementation technology. The paper first summarizes the theoretical background of the KLT feature tracking algorithm. Then hardware-software partition alternatives are evaluated in more detail resulting in FPGA implementations optimizing speed and cost. The pipeline structure of the hardware proved to be necessary due of the great amount of data which should be processed continuously as fast as possible. This work has been motivated by various real-time applications described in other papers. [8], [9]. bibtex

  @INPROCEEDINGS{4481267,
   author = {Arató, Péter and Kocza, Gábor and Loványi, István and Vajta, László},
   booktitle = {Intelligent Engineering Systems, 2008. INES 2008. International Conference on}, title={Hardware-software Codesing of Feature Tracking Algorithms},
   year = {2008},
   month = {feb.},
   volume = {},
   number = {},
   pages = {41 -45},
   abstract = {Relative motion of camera and environment results in such visual cues, which may characterize 3D motion as well as the 3D structure of the a-priori unknown environment. 3D navigation includes both tasks: motion and 3D structure estimation. Earlier we showed that navigation can be based on the KLT algorithm where feature-type visual cues (e.g. corners) are selected and tracked throughout the video frame sequence. Reliability and real-time feature of 3D reconstruction mainly depends on the specificities of selected algorithms and design metrics of implementation technology. The paper first summarizes the theoretical background of the KLT feature tracking algorithm. Then hardware-software partition alternatives are evaluated in more detail resulting in FPGA implementations optimizing speed and cost. The pipeline structure of the hardware proved to be necessary due of the great amount of data which should be processed continuously as fast as possible. This work has been motivated by various real-time applications described in other papers. [8], [9].},
   keywords = {3D navigation;3D structure estimation;KLT algorithm;camera motion;cost optimization;feature tracking algorithms;field programmable gate arrays;hardware-software codesign;pipeline structure;speed optimization;hardware-software codesign;sensor fusion;},
   doi = {10.1109/INES.2008.4481267},
   ISSN = {},
  }

• Péter Arató, Bence Csák (2004) Solutions for competition cases in C-language defined application specific hardware. In Computational Cybernetics, 2004. ICCC 2004. Second IEEE International Conference on. pp. 53 -57. doi abstract This paper examines different solutions to arbitrate competition cases in C-language defined application specific hardware. The C to VHDL conversion referred here requires paralleling and allocation techniques, which make it economical with little speed penalty. Four solutions are discussed, advantages and disadvantages compared bibtex

  @INPROCEEDINGS{1437666,
  author={Péter Arató and Bence Csák},
  booktitle={Computational Cybernetics, 2004. ICCC 2004. Second IEEE International Conference on}, title={Solutions for competition cases in C-language defined application specific hardware},
  year={2004},
  month={},
  volume={},
  number={},
  pages={53 -57},
  abstract={This paper examines different solutions to arbitrate competition cases in C-language defined application specific hardware. The C to VHDL conversion referred here requires paralleling and allocation techniques, which make it economical with little speed penalty. Four solutions are discussed, advantages and disadvantages compared},
  keywords={C-language;VHDL conversion;allocation techniques;application specific hardware;arbitrate competition cases;paralleling techniques;C++ language;hardware description languages;hardware-software codesign;},
  doi={10.1109/ICCCYB.2004.1437666},
  ISSN={},}

• Péter Arató, András Orbán, Zoltán Ádám Mann (2003) Component-Based Hardware/Software Co-Design. web _ bibtex

  @INPROCEEDINGS{Arató03component-basedhardware/software,
   author = {Péter Arató and András Orbán and Zoltán Ádám Mann},
   title = {Component-Based Hardware/Software Co-Design},
   year = {2003},
   url = {http://www.cs.bme.hu/~manusz/publications/ARCS-2004/Arato_Mann_Orban_ARCS_2004.pdf}
  }

• P. Arato, S. Juhasz, Z.A. Mann, A. Orban, D. Papp (sept. 2003) Hardware-software partitioning in embedded system design. In Intelligent Signal Processing, 2003 IEEE International Symposium on. pp. 197 - 202. doi abstract One of the most crucial steps in the design of embedded systems is hardware-software partitioning, i.e. deciding which components of the system are implemented in hardware and which ones in software. Different versions of the partitioning problem are defined, corresponding to real-time systems, and cost-constrained systems, respectively. The authors provide a formal mathematic analysis of the complexity of the problems: it is proven that they are NP-hard in the general case, and some efficiently solvable special cases are also presented. An ILP (integer linear programming) based approach is presented that are solving the problem optimally even for quite big systems, and a genetic algorithm (GA) that finds near-optimal solutions for even larger systems. A specialty of the GA is that nonvalid individuals are also allowed, but punished by the fitness function. bibtex

  @INPROCEEDINGS{1275838,
  author={Arato, P. and Juhasz, S. and Mann, Z.A. and Orban, A. and Papp, D.},
  booktitle={Intelligent Signal Processing, 2003 IEEE International Symposium on}, title={Hardware-software partitioning in embedded system design},
  year={2003},
  month={sept.},
  volume={},
  number={},
  pages={ 197 - 202},
  abstract={ One of the most crucial steps in the design of embedded systems is hardware-software partitioning, i.e. deciding which components of the system are implemented in hardware and which ones in software. Different versions of the partitioning problem are defined, corresponding to real-time systems, and cost-constrained systems, respectively. The authors provide a formal mathematic analysis of the complexity of the problems: it is proven that they are NP-hard in the general case, and some efficiently solvable special cases are also presented. An ILP (integer linear programming) based approach is presented that are solving the problem optimally even for quite big systems, and a genetic algorithm (GA) that finds near-optimal solutions for even larger systems. A specialty of the GA is that nonvalid individuals are also allowed, but punished by the fitness function.},
  keywords={ NP-hard complexity; cost-constraint system; embedded system design; genetic algorithm; graph partitioning; hardware-software codesign; hardware-software partitioning; integer linear programming; real-time system; computational complexity; embedded systems; genetic algorithms; hardware-software codesign; integer programming; linear programming;},
  doi={10.1109/ISP.2003.1275838},
  ISSN={},}

• Péter Arató, Tibor Kandár (sept. 2003) Systematic VHDL code generation using pipeline operations produced by high level synthesis. In Intelligent Signal Processing, 2003 IEEE International Symposium on. pp. 191 - 196. doi abstract We present a method for systematic VHDL code generation from a data-flow representation. In such cases, a methodology is needed that yields a hardware description, which are synthetized and mapped into an FPGA. This procedure speeds up the development of the prototype, reduces the time-to-market, and helps the logic and timing simulation. bibtex

  @INPROCEEDINGS{1275837,
  author={Arató, Péter and Kandár, Tibor},
  booktitle={Intelligent Signal Processing, 2003 IEEE International Symposium on}, title={Systematic VHDL code generation using pipeline operations produced by high level synthesis},
  year={2003},
  month={sept.},
  volume={},
  number={},
  pages={ 191 - 196},
  abstract={ We present a method for systematic VHDL code generation from a data-flow representation. In such cases, a methodology is needed that yields a hardware description, which are synthetized and mapped into an FPGA. This procedure speeds up the development of the prototype, reduces the time-to-market, and helps the logic and timing simulation.},
  keywords={ FPGA; data-flow representation; field programmable gate arrays; high level synthesis; logic simulation; pipeline operation; system-level synthesis; systematic VHDL code generation; data flow graphs; field programmable gate arrays; hardware description languages; high level synthesis; pipeline processing; program compilers;},
  doi={10.1109/ISP.2003.1275837},
  ISSN={},}

• Péter Arató, Bence Csák (sept. 2003) Programming language based definition of application oriented hardware. In Intelligent Signal Processing, 2003 IEEE International Symposium on. pp. 185 - 190. doi abstract We present a methodology of how application specific hardware is defined using slightly limited C-language source code. The method is based on corresponding state-machines to each C-language statement, operation, and variable access and chain them by handshaking signals. Optimization steps make high-level parallelism possible without special instructions. Allocation and scheduling make a final compromise between speeds and cost possible. A signal processing example shows the features. bibtex

  @INPROCEEDINGS{1275836,
  author={Arató, Péter and Csák, Bence},
  booktitle={Intelligent Signal Processing, 2003 IEEE International Symposium on}, title={Programming language based definition of application oriented hardware},
  year={2003},
  month={sept.},
  volume={},
  number={},
  pages={ 185 - 190},
  abstract={ We present a methodology of how application specific hardware is defined using slightly limited C-language source code. The method is based on corresponding state-machines to each C-language statement, operation, and variable access and chain them by handshaking signals. Optimization steps make high-level parallelism possible without special instructions. Allocation and scheduling make a final compromise between speeds and cost possible. A signal processing example shows the features.},
  keywords={ C-language source code; application oriented hardware; handshaking signal; hardware-software codesign; high level synthesis; programming language; C language; finite state machines; hardware description languages; hardware-software codesign;},
  doi={10.1109/ISP.2003.1275836},
  ISSN={},}

• Péter Arató, Zoltan Ádám Mann, Zoltan Dm Mann, András Orbán (2003) Hardware-Software Co-Design for Kohonen's Self-Organizing Map. web _ bibtex

  @INPROCEEDINGS{Arató03hardware-softwareco-design,
   author = {Péter Arató and Zoltan Ádám Mann and Zoltan Dm Mann and András Orbán},
   title = {Hardware-Software Co-Design for Kohonen's Self-Organizing Map},
   year = {2003},
   url = {http://www.cs.bme.hu/~manusz/publications/INES-2003/ines.pdf}
  }

• P. Arato, A. Rucinski, I. Jankovitz (jun-1 jul 1994) Time scaled high-level synthesis for pipelined data-flow structures. In Test Workshop, 1994. ATW '94. The Third Annual Atlantic. pp. t-1 -t-6. doi _ bibtex

  @INPROCEEDINGS{747846, 
   author = {Arato, P. and Rucinski, A. and Jankovitz, I.}, 
   booktitle = {Test Workshop, 1994. ATW '94. The Third Annual Atlantic}, 
   title = {Time scaled high-level synthesis for pipelined data-flow structures}, 
   year = {1994}, 
   month = {jun-1 jul}, 
   volume = {}, 
   number = {}, 
   pages = {t-1 -t-6}, 
   keywords = {}, 
   doi = {10.1109/ATW.1994.747846}, 
   ISSN = {},
  }

Master's Theses (3)

• Judit Knoll (2018) Statikus kódelemzés forráskódok szintaktikai és szemantikai modellje alapján . web _ bibtex

  @MastersThesis{kjdiploma,
   title = {Statikus kódelemzés forráskódok szintaktikai és szemantikai modellje alapján  },
   author = {Knoll, Judit},
   school = {Budapest University of Technology and Economics},
   year = {2018},
   url = {https://diplomaterv.vik.bme.hu/hu/Theses/Statikus-kodelemzes-forraskodok-szintaktikai},
  }

• Tamás Alfréd Zsoldos (2015) C forráskódból adatfolyamgráf előállítása (BSc szakdolgozat). web _ bibtex

  @MastersThesis{zstdiploma,
   title = {C forráskódból adatfolyamgráf előállítása (BSc szakdolgozat)},
   author = {Zsoldos, Tamás Alfréd},
   school = {Budapest University of Technology and Economics},
   year = {2015},
   url = {https://diplomaterv.vik.bme.hu/hu/Theses/C-forraskodbol-adatfolyamgraf-eloallitasa},
  }

• Gergely Suba (2011) Funkcionális nyelven leírt algoritmusok alapján VHDL leírás automatikus generálása. web _ bibtex

  @MastersThesis{sgdiploma,
   title = {Funkcionális nyelven leírt algoritmusok alapján VHDL leírás automatikus generálása},
   author = {Suba, Gergely},
   school = {Budapest University of Technology and Economics},
   year = {2011},
   url2 = {https://diplomaterv.vik.bme.hu/Theses/Funkcionalis-nyelven-leirt-algoritmusok-alapjan},
   url = {http://hls.iit.bme.hu/lib/exe/fetch.php/doc/diplomaterv_suba_gergely_2oldal.pdf}
  }

Miscellaneous (3)

• Judit Knoll (2018) Modellalapú statikus kódanalízis biztonságkritikus rendszerek fejlesztéséhez. Budapest University of Technology and Economics. Scientific student circles (TDK) 2018. web _ bibtex

  @misc{Knoll2018,
  author = {Knoll, Judit},
  institution = {Budapest University of Technology and Economics},
  keywords = {TDK},
  mendeley-tags = {TDK},
  publisher = {Scientific student circles (TDK) 2018},
  title = {{Modellalapú statikus kódanalízis biztonságkritikus rendszerek fejlesztéséhez}},
  year = {2018},
  url = {http://tdk.bme.hu/VIK/Szimu1/Modellalapu-statikus-kodanalizis},
  }

• Gergely Suba (2011) Új módszer algoritmusok VHDL-be történő transzformációjára Haskell funkcionális nyelvből kiindulva. Budapest University of Technology and Economics. Scientific student circles (TDK) 2011. web _ bibtex

  @misc{Suba2011,
  author = {Suba, Gergely},
  institution = {Budapest University of Technology and Economics},
  keywords = {TDK},
  mendeley-tags = {TDK},
  publisher = {Scientific student circles (TDK) 2011},
  title = {{Új módszer algoritmusok VHDL-be történő transzformációjára Haskell funkcionális nyelvből kiindulva}},
  year = {2011},
  url = {http://tdk.bme.hu/VIK/Beagyazott-rendszerek/Uj-modszer-algoritmusok},
  }

• Orbán András, Mann Zoltán Ádám (2000) Új ütemező algoritmusok a magas szintű szintézisben. Budapest University of Technology and Economics. Scientific student circles (TDK) 2000. web _ bibtex

  @misc{Andras2000,
  title = {{Új ütemező algoritmusok a magas szintű szintézisben}},
  author = {András, Orbán and Ádám, Mann Zoltán},
  url = {http://www.cs.bme.hu/~mann/publications/TDK-2000-HLS/Mann_Orban_TDK_2000.pdf},
  institution = {Budapest University of Technology and Economics},
  publisher = {Scientific student circles (TDK) 2000},
  year = {2000}
  }

Dissertations (6)

• György Rácz (2018) Új tervezési keretrendszer heterogén többprocesszoros architektúrák rendszer szintű szintéziséhez. web _ bibtex

  @phdthesis{racz,
   title = {Új tervezési keretrendszer heterogén többprocesszoros architektúrák rendszer szintű szintéziséhez},
   author = {Rácz, György},
   school = {Budapest University of Technology and Economics},
   year = {2018},
   url = {http://www.omikk.bme.hu/collections/phd/Villamosmernoki_es_Informatikai_Kar}
  }

• Gergely Suba (2018) Modellalapú új módszer heterogén többprocesszoros architektúrák rendszerszintű szintéziséhez. web _ bibtex

  @phdthesis{suba,
   title = {Modellalapú új módszer heterogén többprocesszoros architektúrák rendszerszintű szintéziséhez},
   author = {Suba, Gergely},
   school = {Budapest University of Technology and Economics},
   year = {2018},
   url = {http://www.omikk.bme.hu/collections/phd/Villamosmernoki_es_Informatikai_Kar}
  }

• György Pilászy (2013) Új algoritmusok a magas szintű szintézis módszertanának kiterjesztésére elosztott rendszerek tervezéséhez és optimalizálásához. web _ bibtex

  @phdthesis{pilaszy,
   title = {Új algoritmusok a magas szintű szintézis módszertanának kiterjesztésére elosztott rendszerek tervezéséhez és optimalizálásához},
   author = {Pilászy, György},
   school = {Budapest University of Technology and Economics},
   year = {2013},
   url = {http://www.omikk.bme.hu/collections/phd/Villamosmernoki_es_Informatikai_Kar/2013/Pilaszy_Gyorgy/ertekezes.pdf}
  }

• Bence Csák (2009) Közvetlen hardver generálás magasszintű nyelvi leírásból. web _ bibtex

  @phdthesis{csakbence,
   title = {Közvetlen hardver generálás magasszintű nyelvi leírásból},
   author = {Csák, Bence},
   school = {Budapest University of Technology and Economics},
   year = {2009},
   url = {http://www.omikk.bme.hu/collections/phd/Villamosmernoki_es_Informatikai_Kar/2009/Csak_Bence/ertekezes.pdf}
  }

• Tibor Kandár (2007) Hierarchikus rendszer-szintű szintézis. web _ bibtex

  @phdthesis{kandartibor,
   title = {Hierarchikus rendszer-szintű szintézis},
   author = {Kandár, Tibor},
   school = {Budapest University of Technology and Economics},
   year = {2007},
   url  = {http://www.omikk.bme.hu/collections/phd/Villamosmernoki_es_Informatikai_Kar/2008/Kandar_Tibor/ertekezes.pdf}
  }

• Zoltán Ádám Mann (2004) Partitioning algorithms for hardware/software co-design. web _ bibtex

  @phdthesis{mannzoltan,
   title = {Partitioning algorithms for hardware/software co-design},
   author = {Mann, Zoltán Ádám},
   school = {Budapest University of Technology and Economics},
   year = {2004},
   url  = {http://www.omikk.bme.hu/collections/phd/Villamosmernoki_es_Informatikai_Kar/2005/Mann_Zoltan_Adam/ertekezes.pdf}
  }

hlsbib bibtpl