Irányítástechnika és Informatika Tanszék

High-level synthesis

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@INPROCEEDINGS{quickcheck, 

  author = {Koen Claessen and John Hughes},
  title = {{QuickCheck}: A Lightweight Tool for Random Testing of Haskell Programs},
  booktitle = {ACM SIGPLAN Notices},
  year = {2000},
  pages = {268--279},
  publisher = {ACM Press}

}

@INPROCEEDINGS{elerea, 

  author = {Gergely Patai},
  title = {Efficient and Compositional Higher-Order Streams},
  booktitle = {Preliminary Proceedings of the 19th International Workshop on Functional and (Constraint) Logic Programming},
  year = {2010},
  pages = {99--113},
  publisher = {Universidad Polit\'{e}cnica de Madrid}

}

@INPROCEEDINGS{yampaarr, 

  author = {Paul Hudak and Antony Courtney and Henrik Nilsson and John Peterson},
  title = {Arrows, Robots, and Functional Reactive Programming},
  booktitle = {Advanced Functional Programming, 4th International School, volume 2638 of LNCS},
  year = {2002},
  pages = {159--187},
  publisher = {Springer-Verlag}

}

@INPROCEEDINGS{yampadep, 

  author = {Neil Sculthorpe and Henrik Nilsson},
  title = {Safe Functional Reactive Programming through Dependent Types},
  booktitle = {Proceedings of the 14th International Conference on Functional Programming ({ICFP} '09)},
  location = {Edinburgh, Scotland},
  publisher = {ACM},
  pages = {23--34},
  year = 2009

}

@INPROCEEDINGS{lucid, 

  author = {Jean-louis Cola\c{c}o and Gr\'{e}goire Hamon and Alain Girault and Marc Pouzet},
  title = {Towards a higher-order synchronous data-flow language},
  booktitle = {EMSOFT'04},
  year = {2004},
  pages = {230--239},
  publisher = {ACM Press}

}

@inproceedings{streamfusion, author = {Coutts, Duncan and Leshchinskiy, Roman and Stewart, Don}, title = {Stream fusion: from lists to streams to nothing at all}, booktitle = {Proceedings of the 12th ACM SIGPLAN international conference on Functional programming}, series = {ICFP '07}, year = {2007}, isbn = {978-1-59593-815-2}, location = {Freiburg, Germany}, pages = {315–326}, numpages = {12}, url = {http://doi.acm.org/10.1145/1291151.1291199}, doi = {http://doi.acm.org/10.1145/1291151.1291199}, acmid = {1291199}, publisher = {ACM}, address = {New York, NY, USA}, keywords = {deforestation, functional programming, program fusion, program optimisation, program transformation}, }

@INPROCEEDINGS{abstr, 

  author = {S. Lindley, P. Wadler, J. Yallop},
  title = {Idioms are oblivious, arrows are meticulous, monads are promiscuous},
  booktitle = {Mathematically Structured Functional Programming},
  year = {2008},
  publisher = {Reykjav\'{i}k University}

}

@INPROCEEDINGS{sharing, 

author = {Andy Gill},
title = {Type-Safe Observable Sharing in {H}askell},
booktitle = {Proceedings of the 2009 {ACM} {SIGPLAN} {H}askell Symposium},
year = {2009},
month = {Sep}

}

@article {arrowcombinators, 

 author = {Sculthorpe, Neil and Nilsson, Henrik},
 affiliation = {School of Computer Science, University of Nottingham, Nottingham, UK},
 title = {Keeping calm in the face of change},
 journal = {Higher-Order and Symbolic Computation},
 publisher = {Springer Netherlands},
 issn = {1388-3690},
 keyword = {Computer Science},
 pages = {227-271},
 volume = {23},
 issue = {2},
 url = {http://dx.doi.org/10.1007/s10990-011-9068-x},
 doi = {10.1007/s10990-011-9068-x},
 abstract = {Functional Reactive Programming (FRP) is an approach to reactive programming where systems are structured as networks of functions operating on signals (time-varying values). FRP is based on the synchronous data-flow paradigm and supports both (an approximation to) continuous-time and discrete-time signals (hybrid systems). What sets FRP apart from most other languages for similar applications is its support for systems with dynamic structure and for higher-order reactive constructs. This paper contributes towards advancing the state of the art of FRP implementation by studying the notion of signal change and change propagation in a setting of structurally dynamic networks of n -ary signal functions operating on mixed continuous-time and discrete-time signals. We first define an ideal denotational semantics (time is truly continuous) for this kind of FRP, along with temporal properties, expressed in temporal logic, of signals and signal functions pertaining to change and change propagation. Using this framework, we then show how to reason about change; specifically, we identify and justify a number of possible optimisations, such as avoiding recomputation of unchanging values. Note that due to structural dynamism, and the fact that the output of a signal function may change because time is passing even if the input is unchanging, the problem is significantly more complex than standard change propagation in networks with static structure.},
 year = {2010}

}

@INPROCEEDINGS{cca, 

  author = {Liu, Hai and Cheng, Eric and Hudak, Paul},
  title = {Causal commutative arrows and their optimization},
  booktitle = {ICFP '09: Proceedings of the 14th ACM SIGPLAN international conference on Functional programming},
  year = {2009},
  isbn = {978-1-60558-332-7},
  pages = {35--46},
  location = {Edinburgh, Scotland},
  publisher = {ACM},
  address = {New York, NY, USA}

}

@MISC{mentorcatapult, 

  howpublished = {\url{http://www.mentor.com/esl/catapult/overview}}

}

@MISC{ctoverilog, 

  howpublished = {\url{http://www.c-to-verilog.com/index.html}}

}

@MISC{impulsec, 

  howpublished = {\url{http://www.impulseaccelerated.com/}}

}

@MISC{b2bits, 

  howpublished = {\url{http://www.b2bits.com/b2bits.html}}

}

@MISC{b2bitsserver, 

  howpublished = {\url{http://www.b2bits.com/trading_solutions/fixedge.html}}

}

@MISC{qwfix, 

  howpublished = {\url{http://qwtradingsystem.com/index.php/Presentation/index.php?option=com_content&task=view&id=1&Itemid=1}}

}

@MISC{qwfixinterface, 

  howpublished = {\url{http://qwtradingsystem.com/index.php/Presentation/index.php?option=com_frontpage&Itemid=1}}

}

@MISC{jettek, 

  howpublished = {\url{http://www.jettekfix.com/node/13}}

}

@MISC{raquantum, 

  howpublished = {\url{http://www.rapidaddition.com/index.asp?page=79}}

}

@MISC{boursetech, 

  howpublished = {\url{http://www.boursetech.com/pdf/bFAST.pdf}}

}

@MISC{openfast, 

  howpublished = {\url{http://www.openfast.org/}}

}

%%%

@INPROCEEDINGS{5433179, author={Kothapalli, K. and Mukherjee, R. and Rehman, M.S. and Patidar, S. and Narayanan, P.J. and Srinathan, K.}, journal={High Performance Computing (HiPC), 2009 International Conference on}, title={A performance prediction model for the CUDA GPGPU platform}, year={2009}, month={dec.}, pages={463 -472}, keywords={CUDA GPGPU platform;CUDA kernel;GPU architecture;NVIDIA;asymptotic analysis;computational power;general purpose programming environments;graphics processing units;histogram generation;list ranking;matrix multiplication;memory access strategy;memory hierarchy;parallel computing platform;parallel supercomputing platform;performance prediction model;pipelining;scheduling;coprocessors;matrix multiplication;memory architecture;parallel architectures;pipeline processing;processor scheduling;programming environments;}, doi={10.1109/HIPC.2009.5433179}, }

@book{1407436, author = {Nguyen, Hubert}, title = {Gpu gems 3}, year = {2007}, isbn = {9780321545428}, publisher = {Addison-Wesley Professional}, }

@manual{CUDA:Programming-Guide, 

  citeulike-article-id = {2667769},
  citeulike-linkout-0 = {http://developer.download.nvidia.com/compute/cuda/1_0/NVIDIA_CUDA_Programming_Guide_1.0.pdf},
  howpublished = {http://developer.download.nvidia.com/compute/cuda/1\_0/NVIDIA\_CUDA\_Programming\_Guide\_1.0.pdf},
  posted-at = {2008-04-14 14:33:30},
  priority = {3},
  title = {NVIDIA CUDA Compute Unified Device Architecture - Programming Guide},
  url = {http://developer.download.nvidia.com/compute/cuda/1_0/NVIDIA_CUDA_Programming_Guide_1.0.pdf},
  year = {2007}

}

@inproceedings{1280110, author = {Sengupta, Shubhabrata and Harris, Mark and Zhang, Yao and Owens, John D.}, title = {Scan primitives for GPU computing}, booktitle = {GH '07: Proceedings of the 22nd ACM SIGGRAPH/EUROGRAPHICS symposium on Graphics hardware}, year = {2007}, isbn = {978-1-59593-625-7}, pages = {97–106}, location = {San Diego, California}, publisher = {Eurographics Association}, address = {Aire-la-Ville, Switzerland, Switzerland}, }

@incollection {1505346, 

 author = {Gutierrez, Eladio and Romero, Sergio and Trenas, Maria and Zapata, Emilio},
 affiliation = {University of Malaga Department of Computer Architecture 29071 Malaga Spain},
 title = {Memory Locality Exploitation Strategies for FFT on the CUDA Architecture},
 booktitle = {High Performance Computing for Computational Science - VECPAR 2008},
 series = {Lecture Notes in Computer Science},
 editor = {Palma, José and Amestoy, Patrick and Daydé, Michel and Mattoso, Marta and Lopes, João},
 publisher = {Springer Berlin / Heidelberg},
 isbn = {978-3-540-92858-4},
 keyword = {Computer Science},
 pages = {430-443},
 volume = {5336},
 url = {http://dx.doi.org/10.1007/978-3-540-92859-1_39},
 doi = {10.1007/978-3-540-92859-1_39},
 abstract = {Modern graphics processing units (GPU) are becoming more and more suitable for general purpose computing due to its growing computational power. These commodity processors follow, in general, a parallel SIMD execution model whose efficiency is subject to a right exploitation of the explicit memory hierarchy, among other factors. In this paper we analyze the implementation of the Fast Fourier Transform using the programming model of the Compute Unified Device Architecture (CUDA) recently released by NVIDIA for its new graphics platforms. Within this model we propose an FFT implementation that takes into account memory reference locality issues that are crucial in order to achieve a high execution performance. This proposal has been experimentally tested and compared with other well known approaches such as the manufacturer’s FFT library.},
 keywords = {Compute Unified Device Architecture (CUDA), Fast Fourier Transform, Graphics Processing Unit (GPU), memory reference locality},
 year = {2008}

}

@techreport{899291, author = {Gibbons, Phillip B. and Matias, Yossi and Ramachandran, Vijaya}, title = {The Queue-Read Queue-Write PRAM Model: Accounting for Contention in ParallelAlgorithms}, year = {1996}, source = {http://www.ncstrl.org:8900/ncstrl/servlet/search?formname=detail\&id=oai%3Ancstrlh%3Autexas_cs%3AUTEXAS_CS%2F%2FCS-TR-96-14}, publisher = {University of Texas at Austin}, address = {Austin, TX, USA}, }

@article{1327492, author = {Dean, Jeffrey and Ghemawat, Sanjay}, title = {MapReduce: simplified data processing on large clusters}, journal = {Commun. ACM}, volume = {51}, number = {1}, year = {2008}, issn = {0001-0782}, pages = {107–113}, doi = {10.1145/1327452.1327492}, publisher = {ACM}, address = {New York, NY, USA}, }

@inproceedings{1454152, author = {He, Bingsheng and Fang, Wenbin and Luo, Qiong and Govindaraju, Naga K. and Wang, Tuyong}, title = {Mars: a MapReduce framework on graphics processors}, booktitle = {PACT '08: Proceedings of the 17th international conference on Parallel architectures and compilation techniques}, year = {2008}, isbn = {978-1-60558-282-5}, pages = {260–269}, location = {Toronto, Ontario, Canada}, doi = {10.1145/1454115.1454152}, publisher = {ACM}, address = {New York, NY, USA}, }

@InProceedings{Hudak2003, 

author =       "Paul Hudak and Antony Courtney and Henrik Nilsson
                and John Peterson",
title =        "Arrows, Robots, and Functional Reactive Programming",
booktitle =    "Summer School on Advanced Functional Programming 2002,
                Oxford University",
year =         2003,
volume =       2638,
series =       "Lecture Notes in Computer Science",
pages =        "159--187",
publisher =    "Springer-Verlag"

}

@article{Hudak96buildingdomain-specific, author = {Hudak, Paul}, title = {Building domain-specific embedded languages}, journal = {ACM Comput. Surv.}, issue_date = {Dec. 1996}, volume = {28}, issue = {4es}, month = {December}, year = {1996}, issn = {0360-0300}, articleno = {196}, url = {http://doi.acm.org/10.1145/242224.242477}, doi = {10.1145/242224.242477}, acmid = {242477}, publisher = {ACM}, address = {New York, NY, USA}, }

@unpublished{lcgk:09, 

  author = {Lee, Sean and Chakravarty, Manuel M. and Grover, Vinod and Keller, Gabriele},
  citeulike-article-id = {3872848},
  keywords = {compiler, functional, parallel},
  posted-at = {2009-01-10 08:09:18},
  priority = {0},
  title = {GPU Kernels as Data-Parallel Array Computations in Haskell},
  year = {2009}

}

@manual{opencl08, 

author = {{Khronos OpenCL Working Group}},
interhash = {523238fb8572f0681867457896fdda6b},
intrahash = {f27b3794b8bb531800e71e0c1bad328f},
title = {The OpenCL Specification, version 1.0.29},
url = {http://khronos.org/registry/cl/specs/opencl-1.0.29.pdf},
year = 2008,
timestamp = {2009.03.08},
keywords = {imported},
added-at = {2009-09-10T14:36:22.000+0200},
owner = {gregor},
biburl = {http://www.bibsonomy.org/bibtex/2f27b3794b8bb531800e71e0c1bad328f/gregoryy},
month = {8 December}

}

@unpublished{svenson, 

author = {Joel Svensson, Mary Sheeran, Koen Claessen},
title = {Obsidian: A Domain Specific Embedded Language for Parallel Programming of Graphics Processors},
year = {2008}

}

@unpublished{fast_prot, author = {FIX Protocol Ltd}, title = {FAST Specification}, year = {2006} }

Eclipse

@misc{eclipsefp, 

  howpublished = {\url{http://eclipsefp.sourceforge.net/}}

}

@misc{xtext, 

  howpublished = {\url{http://www.eclipse.org/Xtext/}}

}

@misc{ecore, 

  howpublished = {\url{http://help.eclipse.org/galileo/index.jsp?topic=/org.eclipse.xtext.doc/help/metamodelInference.html}}

}

@misc{emf, 

  howpublished = {\url{http://www.eclipse.org/modeling/emf/}}

}

@misc{gmp, 

  howpublished = {\url{http://www.eclipse.org/modeling/gmp/}}

}

@misc{veditor, 

  howpublished = {\url{http://veditor.sourceforge.net/}}

}

FPGA

@techreport{ieee1076, Author = {ISO/IEC}, Institution = {Institute of Electrical and Electronics Engineers, Computer Society}, Month = {26. January}, Title = {IEEE 1076-2008: IEEE Standard VHDL Language Reference Manual}, Year = {2009} }

TODO

@ARTICLE{5981354, author={}, journal={IEEE Std 1076-2008 (Revision of IEEE Std 1076-2002) - Redline}, title={IEEE Standard VHDL Language Reference Manual - Redline}, year={2009}, month={26}, volume={}, number={}, pages={1 -620}, abstract={Replaced by IEC 61691-1-1 Ed.2 (2011-05). VHSIC Hardware Description Language (VHDL) is defined. VHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. Its primary audiences are the implementors of tools supporting the language and the advanced users of the language.}, keywords={}, doi={}, ISSN={},}

@misc{xilinxsdk, 

  howpublished = {\url{http://www.xilinx.com/tools/sdk.htm}}

}

@misc{vhdltutorial, 

         title = {VHDL Tutorial},
          note = {\url{http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html}}

}

@misc{mentorgr, 

  howpublished = {\url{http://www.mentor.com/products/fpga/products}}

}

@misc{cadence, 

  howpublished = {\url{http://www.cadence.com/products/ld/Pages/default.aspx}}

}

@misc{xilinx, 

  howpublished = {\url{http://www.xilinx.com/tools/designtools.htm}}

}

@misc{virtex, 

  howpublished = {\url{http://www.xilinx.com/products/devkits/EK-V6-ML605-G.htm}}

}

@misc{altera, 

  howpublished = {\url{http://www.altera.com/products/devkits/stratix-index.jsp}}

}

@misc{alterafp, 

  howpublished = {\url{http://www.eetimes.com/design/programmable-logic/4207687/How-to-achieve-1-trillion-floating-point-operations-per-second-in-an-FPGA}}

}

@misc{impulse, 

  howpublished = {\url{http://infpga.com/news/2010/9/14/trade-response-latency-reduced-to-under-two-microseconds-by.html}}

}

@misc{s3eboard, 

  howpublished = {\url{http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,792&Prod=S3EBOARD}}

}

@misc{mpwafer, 

  howpublished = {\url{http://www.mimos.my/technology-for-industries/mimos-wafer-fab/multi-project-wafer-mpw-programme/}}

}

@misc{mpwaferserv, 

  howpublished = {\url{http://www.smics.com/website/enVersion/DS/mpWaferService.htm}}

}

@misc{mcpic32, 

  howpublished = {\url{http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=2615&dDocName=en532453}}

}

@misc{analogezkit, 

  howpublished = {\url{http://www.analog.com/en/embedded-processing-dsp/tigersharc/ts201-hardware/processors/product.html}}

}

@misc{fpgaesoc, 

  howpublished = {\url{http://www.silica.com/products/highlight/product/xilinxR-spartanR-6-lx16-evaluation-kit.html}}

}

@misc{microblaze, 

  howpublished = {\url{http://www.xilinx.com/tools/microblaze.htm}}

}

@misc{fixvendors, 

  howpublished = {\url{http://www.fixprotocol.org/products/11}}

}

@misc{onixs, 

  howpublished = {\url{http://www.onixs.biz/selfConnect/cpp/}}

}

Reconfigurable Computing

@article{europeanaccel, author = {N. A. Woods}, title = {FPGA Acceleration of European Options Pricing}, year = {2008}, publisher = {Xtreme Data Inc.} }

@INPROCEEDINGS{americanreconf, author={Wynnyk, C. and Magdon-Ismail, M.}, booktitle={Computational Science and Engineering, 2009. CSE '09. International Conference on}, title={Pricing the American Option Using Reconfigurable Hardware}, year={2009}, month={aug.}, volume={2}, pages={532 -536}, abstract={We present a novel reconfigurable hardware architecture for accelerating American option pricing using the binomial lattice algorithm. The architecture provides double precision floating point pricing, evaluating up to N = 64,000 time steps in the binomial lattice. Advanced memory management techniques and optimized control logic allow for 4-way parallelism on a single-asset evaluation. These techniques achieve a 73-times speedup over an optimized CPU implementation, and a considerable improvement over the best previous reconfigurable hardware implementation. A significant advantage of our approach is that the speed up is on a per asset basis whereas all previous approaches on FPGA and GPU architectures achieve their speed up by evaluating many assets in parallel.}, keywords={4-way parallelism;American option pricing;FPGA architecture;GPU architecture;binomial lattice algorithm;double precision floating point pricing;memory management technique;optimized CPU implementation;optimized control logic;reconfigurable hardware architecture;single-asset evaluation;field programmable gate arrays;financial data processing;floating point arithmetic;parallel algorithms;pricing;share prices;storage management;}, doi={10.1109/CSE.2009.496},}

GHC

@article{haskell98, 

author = {Simon {Peyton Jones} and others},
title = {The {Haskell} 98 Language and Libraries: The Revised Report},
journal = {Journal of Functional Programming},
volume = 13,
number = 1,
pages = {0--255},
month = {Jan},
year = 2003,
url = {http://www.haskell.org/definition/},
doi = {10.1017/S0956796803000315},

}

@article{GHCinliner, author = {Peyton Jones, Simon and Marlow, Simon}, title = {Secrets of the Glasgow Haskell Compiler inliner}, journal = {J. Funct. Program.}, volume = {12}, issue = {5}, month = {July}, year = {2002}, issn = {0956-7968}, pages = {393–434}, numpages = {42}, url = {http://portal.acm.org/citation.cfm?id=968417.968422}, doi = {10.1017/S0956796802004331}, acmid = {968422}, publisher = {Cambridge University Press}, address = {New York, NY, USA}, }

@article{metaprog, author = {Sheard, Tim and Jones, Simon Peyton}, title = {Template meta-programming for Haskell}, journal = {SIGPLAN Not.}, volume = {37}, issue = {12}, month = {December}, year = {2002}, issn = {0362-1340}, pages = {60–75}, numpages = {16}, url = {http://doi.acm.org/10.1145/636517.636528}, doi = {10.1145/636517.636528}, acmid = {636528}, publisher = {ACM}, address = {New York, NY, USA}, keywords = {Meta programming, templates}, }

@misc{haskell2010, 

  author = {Simon Marlow},
  title = {Haskell 2010 Language Report},
  year = {2010},
  url = {http://www.haskell.org/definition/haskell2010.pdf},

}

@misc{ghcusersguide, 

         title = {The Glorious Glasgow Haskell Compilation System User's Guide, Version 6.12.2},
        author = {The GHC Team},
           url = {http://www.haskell.org/ghc/docs/6.12.2/html/users_guide}

}

@misc{ghccore, 

  author = {Andrew Tolmach},
  title = {An External Representation for the GHC Core Language},
  year = {2009},
  url = {http://www.haskell.org/ghc/docs/6.10.4/html/ext-core/core.pdf},

}

@misc{ghcperformance, 

  howpublished = {\url{http://www.haskell.org/haskellwiki/Performance/GHC}}

}

@misc{prelude, 

  howpublished = {\url{http://haskell.org/ghc/docs/6.12.2/html/libraries/base-4.2.0.1/Prelude.html}}

}

@misc{mp3haskell, 

  howpublished = {\url{http://blog.bjrn.se/2008/10/lets-build-mp3-decoder.html}}

}

@misc{ghc, 

  howpublished = {\url{http://www.haskell.org/}}

}

Functional

@book{csornyeilambda, 

title={Lambda-kalkulus},
author={Zolt{\'a}n, Cs{\"o}rnyei},
isbn={9789639664463},
url={http://books.google.hu/books?id=3TI6EYCxTmoC},
year={2007},
publisher={Typotex}

}

@article{csp1, author = {Hoare, C. A. R.}, title = {Communicating sequential processes}, journal = {Commun. ACM}, volume = {21}, issue = {8}, month = {August}, year = {1978}, issn = {0001-0782}, pages = {666–677}, numpages = {12}, url = {http://doi.acm.org/10.1145/359576.359585}, doi = {10.1145/359576.359585}, acmid = {359585}, publisher = {ACM}, address = {New York, NY, USA}, keywords = {classes, concurrency, conditional critical regions, coroutines, data representations, guarded commands, input, iterative arrays, monitors, multiple entries, multiple exits, nondeterminacy, output, parallel programming, procedures, program structures, programming, programming languages, programming primitives, recursion}, }

@book{csp2, author = {C. A. R. Hoare}, title = {Communicating Sequential Processes}, year = {1985-2004}, publisher = {Prentice Hall}, url = {http://www.usingcsp.com/}, howpublished = {\url{http://www.usingcsp.com/}} }

@article{supercompilation2, author = {Mitchell, Neil}, title = {Rethinking supercompilation}, journal = {SIGPLAN Not.}, issue_date = {September 2010}, volume = {45}, issue = {9}, month = {September}, year = {2010}, issn = {0362-1340}, pages = {309–320}, numpages = {12}, url = {http://doi.acm.org/10.1145/1932681.1863588}, doi = {10.1145/1932681.1863588}, acmid = {1863588}, publisher = {ACM}, address = {New York, NY, USA}, keywords = {haskell, optimisation, supercompilation}, }

@article{turchin, author = {Turchin, Valentin F.}, title = {The concept of a supercompiler}, journal = {ACM Trans. Program. Lang. Syst.}, volume = {8}, issue = {3}, month = {June}, year = {1986}, issn = {0164-0925}, pages = {292–325}, numpages = {34}, url = {http://doi.acm.org/10.1145/5956.5957}, doi = {10.1145/5956.5957}, acmid = {5957}, publisher = {ACM}, address = {New York, NY, USA}, }

@article{thunks, author = {Ingerman, P. Z.}, title = {Thunks: a way of compiling procedure statements with some comments on procedure declarations}, journal = {Commun. ACM}, issue_date = {Jan. 1961}, volume = {4}, issue = {1}, month = {January}, year = {1961}, issn = {0001-0782}, pages = {55–58}, numpages = {4}, url = {http://doi.acm.org/10.1145/366062.366084}, doi = {10.1145/366062.366084}, acmid = {366084}, publisher = {ACM}, address = {New York, NY, USA}, }

@article{lambda1, author = {Henk Barendregt and Erik Barendsen}, title = {Introduction to Lambda Calculus}, year = {1994}, masid = {282375} }

@article{callbyneed1, author = {Ariola, Zena M. and Felleisen, Matthias}, title = {The call-by-need lambda calculus}, journal = {J. Funct. Program.}, volume = {7}, issue = {3}, month = {May}, year = {1997}, issn = {0956-7968}, pages = {265–301}, numpages = {37}, url = {http://portal.acm.org/citation.cfm?id=969886.969888}, doi = {10.1017/S0956796897002724}, acmid = {969888}, publisher = {Cambridge University Press}, address = {New York, NY, USA}, }

@inproceedings{recursion1, author = {Edwards, Stephen A. and Zeng, Jia}, title = {Static elaboration of recursion for concurrent software}, booktitle = {Proceedings of the 2008 ACM SIGPLAN symposium on Partial evaluation and semantics-based program manipulation}, series = {PEPM '08}, year = {2008}, isbn = {978-1-59593-977-7}, location = {San Francisco, California, USA}, pages = {71–80}, numpages = {10}, url = {http://doi.acm.org/10.1145/1328408.1328420}, doi = {10.1145/1328408.1328420}, acmid = {1328420}, publisher = {ACM}, address = {New York, NY, USA}, keywords = {SHIM, concurrency, partial evaluation, recursion, static elaboration}, }

@article{recursion2, title = „FPGA-based implementation of recursive algorithms”, journal = „Microprocessors and Microsystems”, volume = „28”, number = „5-6”, pages = „197 - 211”, year = „2004”, notes = ”<ce:title>Special Issue on FPGAs: Applications and Designs</ce:title>”, issn = „0141-9331”, doi = „10.1016/j.micpro.2004.03.008”, url = „http://www.sciencedirect.com/science/article/pii/S0141933104000201”, author = „Valery and Sklyarov”, keywords = {„Recursive algorithms”, „Hierarchical finite state machines”, „Sorting”, „Binary tree”, „Data compression”}, }

HLS

@book{arato, author = {Arato, Peter and Tamas, Visegrady and Jankovits, Istvan}, title = {High Level Synthesis of Pipelined Datapaths}, year = {2001}, isbn = {0471495824}, publisher = {John Wiley \& Sons, Inc.}, address = {New York, NY, USA}, url = {http://dl.acm.org/citation.cfm?id=558618}, }

@phdthesis{csakbence, 

         title = {Közvetlen hardver generálás magasszintű nyelvi leírásból},
        author = {Csák Bence},
        school = {Budapest University of Technology and Economics},
          year = {2009},

}

@book{highlevelsynthesis, author = {Gajski, Daniel D. and Dutt, Nikil D. and Wu, Allen C.-H. and Lin, Steve Y.-L.}, title = {High-level synthesis: introduction to chip and system design}, year = {1992}, isbn = {0-7923-9194-2}, publisher = {Kluwer Academic Publishers}, address = {Norwell, MA, USA}, url = {http://dl.acm.org/citation.cfm?id=129337}, }

Functional HLS

@article{lava, author = {Bjesse, Per and Claessen, Koen and Sheeran, Mary and Singh, Satnam}, title = {Lava: hardware design in Haskell}, journal = {SIGPLAN Not.}, volume = {34}, issue = {1}, month = {September}, year = {1998}, issn = {0362-1340}, pages = {174–184}, numpages = {11}, url = {http://doi.acm.org/10.1145/291251.289440}, doi = {10.1145/291251.289440}, acmid = {289440}, publisher = {ACM}, address = {New York, NY, USA}, }

@inproceedings{ruby, author = {Guo, Shaori and Luk, Wayne}, title = {Compiling Ruby into FPGAs}, booktitle = {Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications}, series = {FPL '95}, year = {1995}, isbn = {3-540-60294-1}, pages = {188–197}, numpages = {10}, url = {http://portal.acm.org/citation.cfm?id=647922.741037}, acmid = {741037}, publisher = {Springer-Verlag}, address = {London, UK}, }

@misc{ruby2, 

  howpublished = {\url{http://www.comlab.ox.ac.uk/geraint.jones/ruby/}}

}

@ARTICLE{lustre, author={Halbwachs, N. and Caspi, P. and Raymond, P. and Pilaud, D.}, journal={Proceedings of the IEEE}, title={The synchronous data flow programming language LUSTRE}, year={1991}, month={sep}, volume={79}, number={9}, pages={1305 -1320}, abstract={The authors describe LUSTRE, a data flow synchronous language designed for programming reactive systems-such as automatic control and monitoring systems-as well as for describing hardware. The data flow aspect of LUSTRE makes it very close to usual description tools in these domains (block-diagrams, networks of operators, dynamical sample-systems, etc.), and its synchronous interpretation makes it well suited for handling time in programs. Moreover, this synchronous interpretation allows it to be compiled into an efficient sequential program. The LUSTRE formalism is very similar to temporal logics. This allows the language to be used for both writing programs and expressing program properties, which results in an original program verification methodology}, keywords={LUSTRE;description tools;program verification methodology;reactive systems;sequential program;synchronous data flow programming language;temporal logics;parallel languages;program verification;temporal logic;}, doi={10.1109/5.97300}, ISSN={0018-9219},}

@misc{ufp, 

         title = {uFP, an algebraic VLSI design language - PhD thesis},
        author = {Mary Sheeran},
          year = {1983},

research_groups = {Programming Research Group, Oxford University} }

@book{ufp2, 

title={Mu FP: an algebraic VLSI design language},
author={Sheeran, M.},
series={Technical monograph},
url={http://books.google.co.uk/books?id=gMtQAAAAIAAJ},
year={1983},
publisher={Oxford University Computing Laboratory, Programming Research Group}

}

@inproceedings{ufp3, author = {Sheeran, Mary}, title = {muFP, a language for VLSI design}, booktitle = {Proceedings of the 1984 ACM Symposium on LISP and functional programming}, series = {LFP '84}, year = {1984}, isbn = {0-89791-142-3}, location = {Austin, Texas, United States}, pages = {104–112}, numpages = {9}, url = {http://doi.acm.org/10.1145/800055.802026}, doi = {10.1145/800055.802026}, acmid = {802026}, publisher = {ACM}, address = {New York, NY, USA}, }

@misc{sasl, 

         title = {Hardware Synthesis from a Stream-Processing Functional Language},
        author = {Simon Frankau},
          year = {2004},
           url = {http://arbitrary.name/papers/}

}

TODO

@inproceedings{sasl11, author = {Frankau, Simon and Mycroft, Alan}, title = {Stream Processing Hardware from Functional Language Specifications}, booktitle = {Proceedings of the 36th Annual Hawaii International Conference on System Sciences (HICSS'03) - Track 9 - Volume 9}, series = {HICSS '03}, year = {2003}, isbn = {0-7695-1874-5}, pages = {278.2–}, url = {http://dl.acm.org/citation.cfm?id=820756.821782}, acmid = {821782}, publisher = {IEEE Computer Society}, address = {Washington, DC, USA}, }

@mastersthesis{clash11, 

        eprintid = {17922},
    howpublished = {http://eprints.eemcs.utwente.nl/17922/},
           month = {December},
          author = {C. P. R. {Baaij}},
       num_pages = {101},
     supervisors = {J. {Kuper} and M. E. T. {Gerards} and E. {Molenkamp} and S. H. {Gerez}},
        keywords = {Hardware Description Languages, Functional Programming, Type Systems},
 research_groups = {EWI-CAES: Computer Architecture for Embedded Systems},
research_programs = {CTIT-WiSe: Wireless and Sensor Systems},
          school = {Univ. of Twente},
           title = {C\ensuremath{\lambda}asH: From Haskell To Hardware},
     institution = {Univ. of Twente},
            year = {2009}

}

TODO

@misc{clash1, 

         month = {December},
         title = {C$\lambda$asH : from Haskell to hardware},
        author = {C. {Baaij}},
          year = {2009},
           url = {http://essay.utwente.nl/59482/},
      abstract = {Functional hardware description languages are a class of hardware description languages that emphasize on the ability to express higher level structural properties, such a parameterization and regularity. Due to such features as higher-order functions and polymorphism, parameterization

in functional hardware description languages is more natural than the parameterization support found in the more traditional hardware description languages, like VHDL and Verilog. We develop a new functional hardware description language, C?asH, that borrows both the syntax and semantics from the general-purpose functional programming language Haskell. In many existing functional hardware description languages, a circuit designer has to use language primitives that are encoded as data-types and combinators within Haskell. In C?asH on the other hand, circuit designers build their circuits using regular Haskell syntax. Where many existing languages encode state using a so-called delay element within the body of a function, C?asH specifications explicitly encode state in the type-signature of a function thereby avoiding the nodesharing problem most other functional hardware description languages face. To cope with the direct physical restrictions of hardware, the familiar dynamically sized lists found in Haskell are replaced with fixed-size vectors. Being in essence a subset of Haskell, C?asH inherits the strong typing system of Haskell. C?asH exploits this typing system to specify the dependently-typed fixed-size vectors, be it that the dependent types are ?fake?. As the designers of Haskell never set out to create a dependently typed language, the fixed-size vector specification suffers slightly from limits imposed by the typing system. Still, the developed fixed-size vector library presents a myriad of functionality to an eventual circuit designer. Besides having support for fixed-size vectors, C?asH also incorporates two integer type primitives. C?asH can be used to develop more than just trivial designs, exemplified by the reduction circuit designed with it. The C?asH design f this reduction circuit runs only 50% slower than a hand-coded optimized VHDL design, even though this first generation C?asH compiler does not have any optimizations whatsoever. With the used FPGA resources being in the same order as the resources used by the hand-coded VHDL we are confident that this first-generation compiler is indeed well behaved. Much has been accomplished with this first attempt at developing a new functional hardware description language, as it already allows us to build more than just trivial designs. There are however many possibilities for future work, the most pressing being able to support recursive functions.} }

@misc{clash2, 

         month = {December},
         title = {Haskell as a higher order structural hardware description language},
        author = {M. {Kooijman}},
          year = {2009},
           url = {http://essay.utwente.nl/59381/}

}

Iparjogvédelem

@misc{liststates, 

  howpublished = {\url{http://www.wipo.int/pct/en/list_states.pdf}},
  url = {http://www.wipo.int/pct/en/list_states.pdf},

}

@misc{szabadalom, 

  howpublished = {\url{http://www.sztnh.gov.hu/szabadalom/}},
  url = {http://www.sztnh.gov.hu/szabadalom/},

}

@misc{szamitogeptalalmany, 

  howpublished = {\url{http://www.sztnh.gov.hu/kiadv/ipsz/200406/01-hamori.html}},
  url = {http://www.sztnh.gov.hu/kiadv/ipsz/200406/01-hamori.html},

}

@misc{torveny1995, 

         title = {1995. évi XXXIII. törvény a találmányok szabadalmi oltalmáról},
          note = {\url{http://www.sztnh.gov.hu/jogforras/1995_XXXIII_Szt.pdf}}

}

Compiler

@MastersThesis{llvmthesis, 

  author  = {Chris Lattner},
  title   = "{LLVM: An Infrastructure for Multi-Stage Optimization}",
  school  = "{Computer Science Dept., University of Illinois at Urbana-Champaign}",
  year    = {2002},
  address = {Urbana, IL},
  month   = {Dec},
  note    = {{\em See {\tt http://llvm.cs.uiuc.edu}.}}

}

nem TODO

@book{lattner2002llvm, 

title={LLVM: an infrastructure for multi-stage optimization},
author={Lattner, C.A.},
url={http://books.google.hu/books?id=jiXJJwAACAAJ},
year={2002},
publisher={University of Illinois at Urbana-Champaign}

}

Dataflow

@book{sriram2009embedded, 

title={Embedded multiprocessors: scheduling and synchronization},
author={Sriram, S. and Bhattacharyya, S.S.},
isbn={9781420048018},
lccn={2008050949},
series={Signal processing and communications},
url={http://books.google.com/books?id=v13bnBCKJLEC},
year={2009},
publisher={CRC Press}

}

@ARTICLE{sdf, author={Lee, E.A. and Messerschmitt, D.G.}, journal={Proceedings of the IEEE}, title={Synchronous data flow}, year={1987}, month={sept.}, volume={75}, number={9}, pages={ 1235 - 1245}, abstract={ Data flow is a natural paradigm for describing DSP applications for concurrent implementation on parallel hardware. Data flow programs for signal processing are directed graphs where each node represents a function and each arc represents a signal path. Synchronous data flow (SDF) is a special case of data flow (either atomic or large grain) in which the number of data samples produced or consumed by each node on each invocation is specified a priori. Nodes can be scheduled statically (at compile time) onto single or parallel programmable processors so the run-time overhead usually associated with data flow evaporates. Multiple sample rates within the same system are easily and naturally handled. Conditions for correctness of SDF graph are explained and scheduling algorithms are described for homogeneous parallel processors sharing memory. A preliminary SDF software system for automatically generating assembly language code for DSP microcomputers is described. Two new efficiency techniques are introduced, static buffering and an extension to SDF to efficiently implement conditionals.}, doi={10.1109/PROC.1987.13876}, ISSN={0018-9219}, }

@article{staticscheduling, author = {Lee, Edward Ashford and Messerschmitt, David G.}, title = {Static scheduling of synchronous data flow programs for digital signal processing}, journal = {IEEE Trans. Comput.}, issue_date = {Jan. 1987}, volume = {36}, issue = {1}, month = {January}, year = {1987}, issn = {0018-9340}, pages = {24–35}, numpages = {12}, url = {http://dx.doi.org/10.1109/TC.1987.5009446}, doi = {10.1109/TC.1987.5009446}, acmid = {22814}, publisher = {IEEE Computer Society}, address = {Washington, DC, USA}, }

@INPROCEEDINGS{multirate, author={Bilsen, G. and Engels, M. and Lauwereins, R. and Peperstraete, J.A.}, booktitle={VLSI Signal Processing, VII, 1994., [Workshop on]}, title={Static scheduling of multi-rate and cyclo-static DSP-applications }, year={1994}, pages={137 -146}, abstract={The high sample-rates involved in many DSP-applications, require the use of static schedulers wherever possible. The construction of static schedules however is classically limited to applications that fit in the synchronous data flow model. In this paper we present cyclo-static data flow as a model to describe applications with a cyclically changing behaviour and build a static schedule for them as well. We also propose a new scheduling method for both multi-rate and cyclo-static applications. Characteristic for this method is that the graph does not need to be transformed into a single-rate equivalent. The new scheduling technique has been implemented in GRAPE-II (Graphical RApid Prototyping Environment)}, keywords={ GRAPE-II; cyclostatic DSP applications; cyclostatic data flow model; graphical rapid prototyping environment; multi-rate DSP applications; multiprocessor environment; static scheduling; synchronous data flow model; signal processing;}, url={http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=574738}, doi={10.1109/VLSISP.1994.574738}, }

@misc{tokenflowmodel, 

  author = {Joseph Buck and Edward A. Lee},
  title = {The Token Flow Model},
  year = {1992}

}

@article{Arató2005665, title = „Time-constrained scheduling of large pipelined datapaths”, journal = „Journal of Systems Architecture”, volume = „51”, number = „12”, pages = „665 - 687”, year = „2005”, issn = „1383-7621”, doi = „10.1016/j.sysarc.2005.02.001”, url = „http://www.sciencedirect.com/science/article/pii/S1383762105000342”, author = „Peter Arato and Zoltan Adam Mann and Andras Orban”, keywords = {„Scheduling”, „High-level synthesis”, „Allocation”, „Pipeline”, „Genetic algorithm”, „Constraint logic programming”}, abstract = „This paper addresses the most crucial optimization problem of high-level synthesis: scheduling. A formal framework is described that was tailored specifically for the definition and investigation of the time-constrained scheduling problem of pipelined datapaths. Theoretical results are presented on the complexity of the problem. Moreover, two new heuristic algorithms are introduced. The first one is a genetic algorithm, which, unlike previous approaches, searches the space of schedulings directly. The second algorithm realizes a heuristic search using constraint logic programming methods. The performance of the proposed algorithms has been evaluated on a set of benchmarks and compared to previous approaches.” }

@INPROCEEDINGS{4481267, author={Arato, P. and Kocza, G. and Lovanyi, I. and Vajta, L.}, booktitle={Intelligent Engineering Systems, 2008. INES 2008. International Conference on}, title={Hardware-software Codesing of Feature Tracking Algorithms}, year={2008}, month={feb.}, pages={41 -45}, abstract={Relative motion of camera and environment results in such visual cues, which may characterize 3D motion as well as the 3D structure of the a-priori unknown environment. 3D navigation includes both tasks: motion and 3D structure estimation. Earlier we showed that navigation can be based on the KLT algorithm where feature-type visual cues (e.g. corners) are selected and tracked throughout the video frame sequence. Reliability and real-time feature of 3D reconstruction mainly depends on the specificities of selected algorithms and design metrics of implementation technology. The paper first summarizes the theoretical background of the KLT feature tracking algorithm. Then hardware-software partition alternatives are evaluated in more detail resulting in FPGA implementations optimizing speed and cost. The pipeline structure of the hardware proved to be necessary due of the great amount of data which should be processed continuously as fast as possible. This work has been motivated by various real-time applications described in other papers. [8], [9].}, keywords={3D navigation;3D structure estimation;KLT algorithm;camera motion;cost optimization;feature tracking algorithms;field programmable gate arrays;hardware-software codesign;pipeline structure;speed optimization;hardware-software codesign;sensor fusion;}, doi={10.1109/INES.2008.4481267}, }